Timing analysis of an optically differential reconfigurable gate array for dynamically reconfigurable processors
Minoru Watanabe, Fuminori Kobayashi · 2004
High-speed reconfigurable processors incorporating a reconfigurable memory and microprocessor array into a chip have been developed [1]. Such devices use a context-switching method. Their internal reconfigurable memory includes reconfiguration contexts of 16 banks. One bank includes a reconfiguration context used for ALUs that can be changed to others on a clock in nanoseconds. These devices have achieved rapid calcula-tion capability using quick reconfiguration. Nevertheless, a problem remains: increasing the amount of in-ternal memory is very difficult while maintaining gate density. An Optical Differential Reconfigurable Gate Array (ODRGA) has been developed to realize both rapid reconfiguration capability and high gate density [2]. ODRGA consists of gate-array VLSI, an external optical memory, and laser light sources. This paper presents timing analysis results for reconfiguration and the execution of ODRGA of when it is used for a dynamically reconfigurable processor. This study obtained both experimental results and HSPICE simulation results. First, the reconfiguration timing was analyzed using a 0.35 µm CMOS process ODRGA-VLSI chip. The reconfiguration time of the ODRGA-VLSI chip is separated into three parts: refresh time, detection time of the optical reconfiguration context, and the response time of differential reconfiguration circuits. The refresh time to fully charge the junction capacitance of photodiodes and the response time of differential reconfiguration circuits were confirmed using HSPICE simulation 1.8 ns and 1.6 ns, respectively. In addition, the photodiode