High-level synthesis for application-specific programmable processors
C. Papachristou, Wei Zhao · 1996
Application Specific Programmable Processors (ASPPs) are processors designed for some applications in a specific domain, such as digital filtering. ASPPs are not like ASICs, which are designed for a single application. ASPPs have wide applications in the field of Digital Signal Processing (DSP). For a lot of DSP applications, it is difficult to give a clear specification at the beginning of the design. A lot of evaluation can only be done when the chip is integrated into the system, when some changes are necessary. To accommodate this kind of late design specification changes, a programmable processor is highly preferred. Also, in many situations, a chip which can implement different functions under different situations has many advantages over several single function ASICs. All of these considerations drive us to study the synthesis of ASPPs. In addition, ASPPs can be used as processor cores to speedup the design of complex chips. In the past years, with the development of VLSI technology, chips have become more and more complex, but, at the same time, design time has decreased dramatically. This challenge forces chip designers not only to move their design from low-level to high-level but also to reuse previous designs. Design with different cores become more and more attractive to chip designers. ASPPs, because of their programmability and highly specific structure, are good candidates for cores. This thesis discusses three different and related aspects of high-level synthesis of ASPPs. In datapath synthesis, we propose an evolution programming approach which can robustly exploit each input behavior's data flow graph space to make the multiple behaviors' descriptions more similar to each other. This approach leads to an optimal area design for the ASPP's datapath. In memory synthesis, we propose a two-stage pipeline architecture for control memory. We also propose a hierarchical clustering approach for the design of this control memory. By exploiting the common control patterns across the control codes for multiple behaviors and saving them in a second stage memory, our approach can reduce the total area of control memory. To synthesize a reuse-friendly core to meet the new challenges in designing a complex chip, the third part of this thesis focuses on synthesis of reuse-friendly ASPP cores. We introduce a usage frequency metric for the RTL core design based on collected multiple behaviors. The RTL components in this RTL core structure are those RTL components that are most commonly shared among all the collected multiple behaviors. The use of this core structure can greatly save time and cost of the overall design process, and it is an important design feature of current design tools. We performed extensive experiments with the help of the tools that we developed and tools that we obtained from our industrial research partner. The experimental results show that our approaches are very encouraging.