CoreSymphony architecture
Tomoyuki Nagatsuka, Yoshito Sakaguchi, Kenji Kise · 2012
We propose CoreSymphony architecture, which aims at balancing single-thread performance and multi-thread performance on CMPs. The former version of CoreSymphony had complex branch predictor, re-order buffer, and in-order state management mechanism. In this paper, we solve these problems and evaluate the performance of CoreSymphony.