Relaxation Based Circuit Simulation Acceleration over CPU-FPGA
Vinay Kumar, Kulshreshth Dhiman, Mandar J. Datar, Akash Pacharne, H. Narayanan, Sachin Patkar · 2016
We present a hardware-software architecture for accelerating point-relaxation based approach to simulation of circuits, where the nonlinear device characteristics can be specified as look-up tables. The approach is shown to be particularly suitable, from a computational perspective, for accelerating variation-aware Monte-Carlo simulations. For each simulation time-step, the approach uses Block Gauss-Seidel or Gauss-Jacobi iterations with Newton-Raphson (NR) iterations for computing node-potentials. The NR iterations are executed on an array of lightweight stack-based processors while the look-up table driven model evaluation requests are scheduled on pipelined bezier interpolation units. Tightly integrated or hybrid CPU-FPGA systems are the ideal targets for this application, however, the architecture was implemented for evaluation in Blue spec System Verilog with SceMI co-emulation on Xilinx Virtex-6 FPGA (ML605 board) hosted on an Intel i7 over PCIe. In our preliminary evaluation over some benchmark circuits, we achieve more than 80% utilization of the 100+ floating-point operators used, amounting to more than 4~GFLOPS computational performance even with the hardware running at 50 MHz.