Microprocessor cores
Andrew Burdass, G. Campbell, Richard Grisenthwaite, David Gwilt, P. Harrod, R. York · 2002
This paper compares and contrast two very different approaches to testing cached CPU macrocells that are typically embedded in a System on Chip (SoC). One uses a test bus to apply functional vectors, while the other uses a combination of scan insertion, memory BIST and test collars. IP protection issues and nonintrusive tracing are also discussed.