Implementation of Self-Checking Carry-Select Adder Based on Two-Rail Encoding in FPGA
Ganekanti Naresh, Praveenkumar, P. · Zenodo (CERN European Organization for Nuclear Research) · 2015
Self-checking carry-select adder design based on two-rail encoding is an efficient method, due to its arithmetic operations and short delay. This paper presents the design of the Compressor based Self-checking carry-select adder design .The circuit can detect all single stuck-at faults during on-line operation mode. Its performance is increased by using compressor by replacing all full adders.