E3R: Energy Efficient Error Recovery for Multi/Triple-Level Cell Non-volatile Memories
Shivam Swami, Kartik Mohanram · 2016
Partial data mapping (PDM) is an effective means to reduce the energy/latency of multi-level/triple-level cell non-volatile memories (MLC/TLC NVMs) by excluding high energy/latency MLC/TLC states. This paper proposes energy efficient error recovery (E3R) to simultaneously extend the lifetime and lower the energy/latency of PDM MLC/TLC NVMs. E3R partitions NVM rows into segments that remain in the PDM mode until a cell failure within a segment. E3R restores the failed segment to the full data mapping (FDM) mode, i.e., Conventional binary mapping, while other segments continue to operate in PDM mode. By incrementally restoring a row from PDM to FDM mode, E3R not only reduces memory energy/latency, but also enhances its lifetime by localizing faults to segments, thereby extending the row error correction capability of error-correcting pointers (ECPs). Simulation results on a TLC RRAM architecture show that E3R improves memory lifetime by 76% in comparison to unprotected memory, while also reducing memory energy by 16% over conventional binary mapping. Furthermore, we propose augmented E3R, which employs residual memory columns from the post manufacturing test to supplement E3R in error recovery. For no additional overhead, augmented E3R further improves memory lifetime by 6.2% over basic E3R.