A Power Efficient Dual Link Mesh NoC Architecture to Support Nonuniform Traffic Arbitration at Routing Logic
Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur · 2016
The pipelined multithreaded server workloads are advent to employ the efficiency of many-core chips. The concurrent transactions of distributed shared caches increase the multicast traffic across the network. Such a hike of traffic directly affects the communication volume of the network. It significantly increases resource consumption and putting pressure on Network on Chip (NoC). So the traditional NoC architectures become the limiting factor for the performance of chips. The state-of-the-art multiplane NoC evolves as a flexible solution to improve performance and power efficiency. It consists of narrower channels and simple routers with multiple independent networks. In this paper, we investigate the multiplane NoC for getting the efficiency of chip multiprocessors. Specifically, we have two contributions in the paper. Firstly, we propose Dual Link Mesh (DLM) (M = 2), a subset of broadly defined multiplane mesh networks (M = N) that can fabricate on a single on-die chip. Secondly, we propose a novel traffic arbitration within NoC at the routing unit, to distribute traffic between mesh networks. Our experiment on PARSEC benchmarks finds 45% efficiency in total router power of the DLM (65nm, 1GHz). The power efficiency approaches 58% as technology shrink to 32nm at 1GHz frequency. In contrast, the power efficiency limits to 40% as frequency increases to 2.5GHz at 65nm technology. Although, the DLM lags behind single plane/link mesh (M = 1) while considering throughput (5%) and latency (4%) that is minor overhead in performance.