High throughput parallel scheme for HEVC deblocking filter
Alaa F. Eldeken, Richard M. Dansereau, Mohamed Mahmoud Fouad, Gouda I. Salama · 2015
In this paper, a new parallel scheme for the deblocking filter (DF) in high efficiency video coding (HEVC) is proposed. This scheme is based on a parallel-straight processing order that improves the performance of HEVC DF. One of the challenges in HEVC is coding time due to computational complexity. Deblocking in HEVC is responsible for nearly 15% of the time consumed while performing video compression. As such, a parallel-straight processing order is introduced that allows improved concurrency for deblocking multiple horizontal and vertical edges. For our examined 4-core case, the approach achieves full utilization of all cores with fewer number of DF steps (i.e., two edges or more) by 27% compared to recent techniques. A four-core parallel architecture is also proposed. This new parallel scheme is implemented on a graphical processing unit (GPU) rather than a CPU to further speed up coding time. Experimental results demonstrate the ability to achieve decoded frame processing times as low as 5.0 ms for All-Intra filtering and 3.0 ms for Low-Delay filtering, corresponding to speedup factors as high as 12 and 7, respectively, compared to the HEVC reference.