Implementation of an FFT Hardware Accelerator for Security Applications
Domenico Argenziano · 2015 10th International Conference on P2P, Parallel, Grid, Cloud and Internet Computing (3PGCIC) · 2015
This work presents the architecture and implementation of a dedicated hardware accelerator for cryptographic purposes. In particular, the paper describes a highly customized FPGA design targeting the most time consuming operation used by the encryption primitives, long-integer multiplication, based on an efficient implementation of the Schonhage-Strassen algorithm (SSA) exploiting the properties of the Discrete Fourier Transform over finite fields. The paper presents the architecture of the accelerator, the details of its implementation, as well as the main performance results.