Why SystemVeriog
Peter L. Flake · Forum on specification and Design Languages · 2013
SystemVerilog is a hardware design and verification language (HDVL) that combines the features of several domain-specific languages for digital hardware design and verification with a general purpose object-oriented programming language. The paper discusses the functional and performance requirements of each domain, and the history of why particular language design choices were made. SystemVerilog is also compared with SystemC and VHDL.