Optimization Design of 24 Bit Parallel MAC Unit with Saturation
Meng Zhang, Junbo Jia · Journal of Southeast University · 2006
An efficient design method for a 24×24 bit + 48 bit parallel saturating multiply-accumulate (MAC) unit is described. The augend in the MAC is merged as a partial product into Wallace tree array. The optimized saturation detection logic is proposed. The 679.2 µm×132.5 µm area size has been achieved in 0.18 µm 1.8 V 1P6M CMOS technology by the full-custom circuit layout design. The simulation results show that the design way has significantly less area (about 23.52% reduction) and less delay than those of the common saturating MAC based on standard cell library.