Thermal-Safe Schedule Generation for System-on-Chip Testing
Rajit Karmakar, Santanu Chattopadhyay · 2016
This paper presents a thermal safe test scheduling strategy for System-on-Chip (SoC). While most of the existing strategies rely on some approximate thermal models to avoid the time consuming online thermal simulations, the present work proposes to use a superposition principle-based thermal model, which can estimate the temperature of the cores quite accurately, yet fast, without invoking thermal simulation inside the schedule generation process. The thermal model, along with a window-based peak power model, has been incorporated into a Particle Swarm Optimization (PSO) based meta search technique to generate the test schedules. In contrast to the existing works, the introduction of new SoC benchmarks with detailed information regarding power and floor plan enables us to observe exact thermal behaviors of the cores. Experimental results on these newly proposed benchmarks show the superiority of our thermal model over the existing ones.