Performance optimization for a SHA-1 cryptographic workload expressed in OpenCL for FPGA execution
Fernando Martinez Vallina, Spenser Gilliland · 2015
The introduction of Field Programmable Gate Array (FPGA) based devices for OpenCL applications provides an opportunity to develop kernels which are executed on application specific compute units which can be optimized for specific workloads such as encryption. This work examines the optimization of the SHA-1 hashing algorithm developed in OpenCL for and FPGA based implementation. The implementation starts from the freely available SHA-1 implementation in OpenSWAN; ports the implementation to OpenCL; and optimizes the kernel for FPGA implementation using the Xilinx SDAcccel development environment for OpenCL applications. Through each stage, the implementation is benchmarked in order to examine latency, throughput, and power usage on FPGA, Graphics Processing Unit (GPU), and Central Processing Unit (CPU) systems.