Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors
Sudarshan Srinivasan, Nithesh Kurella, Israel Koren, Sandip Kumar Kundu · 2016
As the processor manufacturers focus on designing performance and power efficient cores, asymmetric multicore processors (AMP) have emerged as a viable option. AMPs include multiple cores with varying power and performance characteristics, allowing a workload to choose the best core for power efficiency, which varies during the course of execution. Naturally, this involves migration of execution across cores, which also entails performance and power overhead. This overhead limits the frequency of migration. Recent papers has proposed the implementation of micro architectural heterogeneity within a core, that makes fine grain switching possible by reducing migration overhead. Another way to implement heterogeneity in core is application of Dynamic Voltage and Frequency Scaling (DVFS). DVFS also involves a transition overhead during which no execution can take place. Recent designs report faster voltage transition and PLL relock time, thus enabling fine grain DVFS. In this work, we study the power efficiency at fine grain switching of a dynamically reconfigurable non-monotonic processor versus pure DVFS. Comparison is extended to a Big/Little processor with both fine and coarse grain switching support.