Genetic algorithm for designing reliable embedded system using IP-Cores not resilient to soft-error
Adeel Israr, Sorin Alexander Huss · 2016
The exponentially decreasing transistor size has resulted in tremendous increase in microprocessor speed, and computational power per dollar. But it has also made the digital logic more susceptible to soft-errors. In this paper we discuss a technique to use the advantages of the shrinking of the feature size to overcome its disadvantages. Each task of a task-graph is implemented as a set of parallel reliability groups (PRG), thus increasing the overall reliability of the system. We develop a genetic algorithm to solve a multi-objective optimization problem, to find the best combination of parallel reliability groups of each task, allocation, binding and scheduling. The results show that larger number of PRGs can improve the reliability of the system working in more error prone environment and small number PRGs can be used for reducing the cost of the system, with negligible loss in the reliability, when the system is working in relatively error-free environment.