Exploiting Low Cost Reliability for NoC Transient Routing Error
Jiajia Jiao, Peng Wu, Yuzhuo Fu · ASME Press eBooks · 2011
In dominant many-core system, NoC (Network on Chip) also requires fault tolerance configuration for dependable communication. Compared with payload error, transient routing error causes fatal problems, such as packets delivered to wrong destination, network deadlock due to routing algorithm or topology forbidden. We propose a light weight redundancy method to solve transient NoC routing error: 1) configuring routing information with TMR (Triple Modular Redundancy) only for head flits; 2) exploiting inherent hardware and time redundancy for reliable routing computation. And the simulation results from cycle accurate platform show that this method brings higher routing error recovery rate with less performance loss and overhead than other fault tolerant mechanisms.