Testing macro-module-based self-timed circuits
Ajay Khoche · 1996
This dissertation addresses the testing problem for a subclass of asynchronous circuits called self-timed circuits. The specific circuits being considered are those built using a library of self-timed modules called macro-modules. It has been shown that the existing approaches do not provide adequate fault coverage. A partial scan technique has been proposed to enhance the fault coverage. Rules for selecting the latches for partial scan have been developed based on the fault analysis of macro-modules. Also circuit modifications have been proposed to test the remaining sequential parts. A new algebra has been developed to generate critical hazard free tests under this partial scan environment. Testing of micropipelines which are self-timed pipelines has also been addressed. A novel scan technique has been developed such that existing wires can be used as scan clock in test mode. Thus it does not require any extra scan clocks be introduced in the circuit. This technique also enables delay fault testing in micropipelines. The basic technique can be extended to incorporate a partial scan. Finally a Design For Testability (DFT) tool called ACT (Asynchronous Circuit Testing) has been developed to implement the partial scan ideas mentioned above. This tool is the first of its kind. It accepts the user's design in schematic form and automatically generates a testable design. Test vectors are then generated for this testable design using a custom test generation system and corresponding fault coverage is computed. The tool is built around the commercial tools from Viewlogic and Cascade and provides a complete path from Schematic capture to physical layout and test vectors with corresponding fault coverages.