HiPAD: High Performance Adaptive Deflection Router for On-Chip Mesh Networks
Simi Zerine Sleeba, John Jose, M. G. Mini · 2015
The efficiency of a router in a Network on Chip (NoC) is characterised by good performance, minimum packet latency, area and power. In this paper, we propose an adaptive deflection router for mesh NoC which offers higher speed of operation by reducing the router critical path latency. We propose a single cycle router that uses an intelligent decision making logic to store deflected flits in minimum number of side buffers. Synthesis results of the design show an overall reduction in timing latency compared to a conventional minimally buffered router with two cycle latency. Network simulation of the proposed architecture using synthetic and real application traffic reports that the average flit latency and deflection rate reduces significantly in our design compared to the state-of-the-art single cycle deflection routers.