Simulation based Performance Study of Cache Coherence Protocols
Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran · 2015
Cache coherence protocol maintains data consistency between different cores / processors in a shared memory multi-core (MC) / multi-processor (MP) system. Coherency can be achieved at the cost of increased miss rate because of invalidations. Coherency misses and the number of signals for maintaining data in consistent state consumes additional time and energy. This paper studies the impact of cache coherence misses, invalidations and additional signals due to MI, MESI and MOESI cache coherence protocols implemented in Gem5 -- the most widely used full system simulator. The experimental studies show that the dynamic energy consumption due to cache miss in MI, MESI and MOESI protocols are 53.6%, 31.2% and 31.1% for 32KB L1 cache and 46.3%, 23.0% and 22.1% for 64KB L1 cache respectively. The average number of signals per access in case of MI, MESI and MOESI protocols is 4.23, 4.16 and 4.19 respectively for SPLASH-2 benchmarks suits.