Intel386 EX embedded processor I/sub DDQ/ testing
Hitesh Ahuja, Dean Arriens, Ben Schneller, V. Verma, Wendy Whitman · 2002
I/sub DDQ/ testing, along with stuck-at fault, AC timing, and DC testing is increasingly considered a necessity for good product quality. This paper presents an I/sub DDQ/ vector selection methodology, along with vector implementation in the production test program. I/sub DDQ/ fault seeding results show that by stuck-at fault modeling, we can detect single stuck-at nodes that were not detected before. A comparative evaluation of conventional testing methods and I/sub DDQ/ testing is presented. Experimental test results are presented that ascertain the effectiveness of I/sub DDQ/ particularly how it overlaps with stuck-at fault coverage. A practical method that estimates the test coverage overlap is applied to reduce the stuck-at improvement effort and obtain "credit" towards the Intel386 EX processor quality requirements for production. A follow-on experiment for obtaining more data is proposed and data are being collected.