Introduction to the Tiled HW Architecture of SHAPES
Pier Stanislao Paolucci, Francesca Lo Cicero, A. Lonardo, Mersia Perra, Davide Rossetti, Carlo Sidore, P. Vicini, Marcello Coppola, Luigi Raffo, Francesca Palumbo, Luca Fanucci, Sergio Saponara, Francesco Vitullo, Infn Roma, Atmel Roma · 2007
Nanoscale systems on chip dedicated to embedded systems and numerical computations will integrate a few hundreds of million gates. The challenge is to find a scalable HW/SW design style for future CMOS technologies. The main HW problem is wiring, which threatens Moore’s law. Tiled architectures suggest a possible HW path: “small” processing tiles connected by “short wires”. A second HW problem is the management of the design complexity. A tiled design style reuses stable Intellectual Properties requiring a few million gates: a manageable complexity. A typical SHAPES tile always contains one Distributed Network Processor (DNP) for inter-tile communications, plus one VLIW DSP processor for computation and/or one RISC processor for control. The DNP is supported by a NoC (for inter-tile, inter-chip communications) and by Ndimensional toroidal network for off-chip communications. The SW challenge is to provide a simple and efficient programming environment for a (massive) tiled parallel architecture. This paper introduces the HW architecture.