Code sharing in FPGA-based Moore FSMs
Jacek Bieganowski, Alexander A. Barkalov, Larysa Titarenko, Wojciech Zając · AIP conference proceedings · 2015
A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with FPGAs. The method is based on the idea of code sharing. The main difference from already known methods is that the counter increases its content during conditional and unconditional transitions. An example of application of proposed method is given.