Mid-level hardware synthesis
Pao-Po Hou · 1991
An approach to synthesis logic from mid-level descriptions is presented in this thesis. The emphasis is put on solving several problems pertinent to the synthesis of VHDL process statements. Issues covered include development of synthesis subsets, semantic bindings of various VHDL language constructs, resolution of data dependencies, identification of state boundaries, separation of control path specifications from data path specifications, and the generation of state tables and the corresponding control networks from control specification. State tables can be processed by various finite state machine analysis tools. Multi-level logic control units are produced. Both synchronous behavior and asynchronous descriptions are treated in this thesis.