Classification of compiler optimizations for high performance, small area and low power in FPGAs
Emre Özer, Andy P. Nisbet, David P. Gregg · e-space (Manchester Metropolitan University) · 2003
We propose a classification of high and low-level compiler optimizations to reduce the clock period, power consumption and area requirements in Field-programmable Gate Array (FPGA) architectures. The potential of each optimization, its effect on clock period, power and area and machine dependency is explained in detail.