24-bit significand multiplier for FPGA floating-point multiplication
E. George Walters · 2015
This paper presents a 24-bit significand multiplier for single-precision floating-point multiplication that is optimized for Xilinx FPGAs with 6-input LUTs. The design combines a 24 × 7 LUT-based multiplier and one embedded multiplier to implement a 24 × 24 unsigned multiplier. The proposed design uses 35% fewer LUTs and is 1.11 times faster than a LogiCORE multiplier that also uses one embedded multiplier. A truncated- matrix version that allows faithful rounding uses 78% fewer LUTs and is 1.17 times faster than a LogiCORE multiplier that uses one embedded multiplier. Both designs are comparable in speed to a LogiCORE multiplier that uses two embedded multipliers.