Fault Collapsing and Test Generation for a Circuit
Moslem Amiri, Václav Přenosil · 2013
A novel method to generate a complete list of faults and their corresponding test vectors for a gate-level circuit is presented. This method creates the distinguishable faults of a circuit based on the paths they propagate, along with the test vector(s) for each fault. While the other available methods for fault list and test vector generation are expensive, this method tries to reduce the cost by avoiding all the unnecessary steps and merging the two tasks together.