An array-based hardware accelerator for digital logic simulation
E. Scott Fehr · 1992
The increasing densities provided by VLSI technology have created a demand for CAD systems capable of quickly simulating and verifying large, complex designs. CAD tools for this class of application can accelerate time-intensive aspects of the simulation process by recognizing design concurrency. Previously, tool development efforts have evolved as either software algorithms implemented on general purpose computers or as special purpose hardware accelerators designed to optimize certain simulation algorithms. This research investigates architectural, as distinguished from algorithmic, speedup potential in simulation acceleration platforms that match digital designs rather than simulation style algorithms. The research thrust is to establish proof of principle for an acceleration architecture that provides state of the art performance while reducing hardware cost by multiple orders of magnitude, thereby greatly improving cost-performance value for hardware acceleration technology. A hardware architecture is proposed which allows direct mapping of design simulation topology onto the acceleration platform. In order to isolate architectural principles for analysis, the simulation is confined to functional verification of unit-delay, binary-valued gate-level logic designs. Under this approach, a levelized design description is executed on a massively parallel processor grid which implements an efficient and direct model of the design, an equivalent of prototyping.