An ASIC implementation of the two-dimensional Discrete Cosine Transform
Feng Chen · ThinkTech (Texas Tech University) · 1996
1|>.>v 5.1 The Timing and control Block 39 5.1.1Control Signals for the ID-DCT 40 5.1.2Control Signals for the Transposition RAM 43 5.1.3Verification of the Timing and Control Unit 43 5.2 The Transposition RAM 47 5.2.1 RAM Array Design 48 5.2.2 Verification of the Transposition RAM 51 5.3 Implementation of the ID-DCT 53 5.3.1 The Input and the Parallel-to-Serial Shift Registers 5 5 5.3.2ROM 58 5.3.3Operative Unit 61 6. CONCLUSIONS 65