Low power VLSI implementation schemes for DCT-based image compression
Shedden Masupe · ERA · 2001
With the ever increasing need for portable electronic devices, there is a growing need for a new look at very large scale integration (VLSI) design in terms of power consumption.Most of the research and development efforts have focused on increasing the speed and complexity of single chip digital systems.In other words, focusing on systems that can perform most computations in given amount of time.However, area and time are not the only metrics that can measure implementation quality.Power consumption has now entered the field, so designers need to take another important parameter as a third dimension in order to enhance the device capabilities.The Discrete Cosine Transform (DCT) is the basis for current video standards like H.261, JPEG and MPEG.Since the DCT involves matrix multiplication, it is a very computationally intensive operation.Matrix multiplication entails repetitive sum of products which are carried out numerous times during the DCT computation.Therefore, as a result of the multiplications, a significant amount of switching activity takes place during the DCT process.This thesis proposes a number of new implementation schemes that reduce the switching capacitance within a DCT processor for either JPEG or MPEG environment.I would also like to thank all the guys in the SLI activity for their continuous assistance in the subject matter of various aspects of the project.In particular, Damon Thompson for his ever keen assistance with VHDL/Verilog programming and nifty digital design tips.I have to thank Dr Ahmet Erdogan for his inspirational assistance in the low power design techniques.Baba Goni, he had so much faith in me even at times that I doubted myself, I appreciate that.I thank Prof Alan F