High level NoC modeling using discrete event simulation
Nejib Mediouni, Samir Ben Abid, Oussama Kallel, Salem Hasnaoui · 2015
Planning and evaluating a Network on Chip (NoC) for a specific application is usually a complex task that requires the collaboration of both hardware and software specialists. Predicting the performance of the devised architecture and solution is both difficult in nature and time consuming. In this paper we present a high level model for five-port router based NoCs using Matlab's SimEvents toolbox. The presented model is used to construct a 4 × 4 mesh NoC and evaluated the usual performance metrics like latency and throughput.