An Efficient Algorithm for Hardware Implementation of Low-Bit-Rate Speech Coding
Hwai-Tsu Hu · 2002
This paper presents an algorithm for hardware implementation of low-bit-rate speech coding. The coding scheme emerges from traditional pitch-excited linear prediction vocoders. While the excitation switches between glottal pulses and random noise according to the voicing condition, the spectral properties are characterized by a prefixed highpass filter in combination with 8th-order cosine functions of LSF parameters, which are attainable by an efficient root-solving method. To make this algorithm suitable for hardware implementation either by ASIC design or by programming on a signal processor, constraints are imposed on the complexity of the algorithm as well as the need of special-purpose arithmetic operations. Nonetheless, the resulting algorithm is still capable of carrying out 1.6 Kbps speech coding with acceptable quality. Informal listening tests reveal that listeners exhibit evident preference for the proposed speech coder over the 2.4 Kbps LPC-10e vocoder, though the overall synthetic quality is somewhat inferior to that of the 4.8 Kbps CELP and 2.4 Kbps MELP vocoders.