A Novel Approach to Block Floating Point Arithmetic for Digital Signal Processor Design
Sridha Sridharan · 1987
Block floating-point arithmetic is considered as an alternative to fixed-point and floating-point arithmetic in the implementation of recursive digital signal processing algorithms. Block floating-point implementation of state-space digital structures is shown to have improved signal-to-noise ratio compared to fixed-point implementation and can be designed to be free of overflow. The maximum amplitude of zero input limit cycle is limited to 1 bit. Architecture suitable for the VLSI implementation of a block floating point co-processor is described.