Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O
Ishita Mukhopadhyay, Mustansir Y. Mukadam, Rajendran Narayanan, Frank O’Mahony, Alyssa Apsel · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2015
In this paper, we propose a dual-calibration technique to improve the matching accuracy of digital-to-analog converter (DAC) elements and improve nonlinearity induced static errors in a current-steering thermometer DAC. The novelty of the proposed dual-calibration scheme lies in obtaining best samples from the error distribution using redundancy for improved matching followed by adaptively reordering these samples to reduce error accumulation. This technique exploits the 2-D nature of the DAC to achieve lower calibration time. We consider the statistical basis for each of these methods and demonstrate statistical modeling of the proposed technique. We demonstrate a 38% reduction in differential nonlinearity (DNL) and 55% reduction in integral nonlinearity (INL) through simulations. We fabricated an 8-bit current steering thermometer DAC in Taiwan Semiconductor Manufacturing Company 65-nm CMOS process. With only 2 redundant cells per row, we show an improvement of 36% in DNL and 50% in INL from the measurement of 16 chips over the baseline DAC.