A VHDL front end
Baokang Chen · Open Collections · 2009
VHDL (the VHSIC Hardware Description Language) is an industry standard language used to describe hardware from the rather abstract behaviors to the very concrete circuits. This thesis is about the design and implementation of a VHDL front end. A brief introduction to VHDL is given with easy-to-understand examples. Our focus of the front end is on type checking and overload resolution in VHDL. Data structures and the approach to parsing VHDL are discussed in detail. We also propose a program interface to the front end and provide users with a set of library routines for further processing of a VHDL program. The application of the front end is illustrated by the elaboration of generate statements.