Experience with the Design of a Special-purpose, Pipe-lined Floating-point Adder Using Field-programmable ASlCs
DG Wong · 1989
The aim of this paper is to describe the design of a special-purpose, pipe-lined, floating-point adder using erasable programmable logic devices (EPLDs). The number format used by the floating-point adder provides the five categories of numbers specified by the I.E.E.E. Standard on Binary, Floating-point Arithmetic, viz: Zeros, Denormalised Numbers, Normalised Numbers, Infinities and Not-a-Number. The design and construction of the floating-point adder have been the objectives of a laboratory assignment for final-year Electrical Engineering students at the University of Sydney. While the assignment has proved to be very challenging, even for the best students, it is considered to have high educational value as it clearly demonstrates the potential of field-programmable Application Specific Integrated Circuits.