FastICA architecture utilizing FPGA and iterative symmetric orthogonalization for multivariate signals
Al-Laith Taha, Luay Yassin Taha, Esam Abdel‐Raheem · 2015
This paper presents an efficient architecture of a fixed-point Fast Independent Component analysis (FastICA) in field programmable gate array (FPGA). The algorithm separates up to four signals using four sensors. A prestage QR decomposition is used to improve the speed of eigenvalues and eigenvectors evaluation of the covariance matrix. Moreover, a symmetric orthogonalization of the unit estimation algorithm is implemented using an iterative technique to speed up the search algorithm for higher order data input. The algorithm is implemented using Xilinx Virtex5-XC5VLX50t FPGA. The proposed architecture can process 128 samples for the four sensors in less than 2.5 ms when the design is simulated using 100 MHz clock.