Area-efficient and power-efficient binary to BCD converters
Srirathan Rangisetti, Ashish Joshi, Tooraj Nikoubin · 2015
This paper presents four novel circuits for 7-bit Binary to BCD conversion. The first and second designs are modification of 3-3-1[1] algorithm with novel building blocks, which makes it area and delay efficient in comparison with previous design. The third circuit is the novel implementation of the shift-add algorithm that makes this design area efficient in compare with existing architectures. The final architecture presented is the implementation of the novel algorithm, which we called Range Detection Algorithm in this paper. This Range Detection circuit is power efficient in comparison with existing architectures. Simulation results specify that these Shift-add and Range Detection designs are area-efficient and power-efficient as there is a significant decrease in area, power, and power-area product.