Hardware implementations of trellis based decoders for linear block codes
E. Leonardi · Lume (Universidade Federal do Rio Grande do Sul) · 2013
Forward error correction based on convolutional codes or block codes is an essential part in today’s communication systems. If convolutional codes are used, mostly the graphical trellis representation of a code is used in decoding. Efficient trellis based decoding algorithms can then be used, such as the Viterbi algorithm (VA)[3] or the maximum a posteriori algorithm (MAP)[4]. However, it is shown in [1] that a linear binary block code can also be represented by a Trellis diagram. Then, the efficient VA and MAP can also be applied to block codes. This work presents two new architectures for the VA and MAP for block codes and their implementation on FPGA. First, we construct a Viterbi decoder and show how a Banyan permutation network can be used to solve the time variance problem of a Trellis diagram for block codes. Afterwards, we use part of the presented to design a MAX-Log- MAP decoder for linear block codes. To our best knowledge they are the first hardware implementations of these kind. We present implementation details for FPGA designs (Xilinx Virtex 6) of VA and MAP decoders for different trellis sizes. The FPGA designs are analyzed and compared, regarding resource consumption and data throughput. For a 64 state trellis the VA consumes 2800 LUTs and achieves a throughput of 140 Mbit/s, the MAP consumes 6800 LUTs at 70 Mbit/s.