Iterative and Fully Pipelined High Throughput Efficient Architectures of AES in FPGA and ASIC
Vijay Kumar Sharma, Saurabh Kumar, Kamalakanta Mahapatra · Journal of Circuits Systems and Computers · 2016
This paper presents high throughput iterative and pipelined VLSI architectures of the Advanced encryption standard (AES) algorithm based on composite field arithmetic in polynomial basis. A logical rearrangement has been performed in the byte substitution (S-box) module to reduce the number of gates in the critical path. Also, inversion in GF(24) module has been separately optimized. ASIC implementation of our S-box has comparatively low power and low energy consumption. The iterative and pipelined implementations of AES in field programmable gate array (FPGA) and ASIC using proposed S-box have high hardware efficiency in terms of throughput per unit area (slices in FPGA).