Optimizing inter-instruction value communication through degree of use prediction
J. Adam Butts, Gurindar S. Sohi · 2004
The design of high-performance value communication structures represents a significant chal-lenge in the implementation of future microprocessors. The complexity of these structures— namely, the register file, the bypass network, and the instruction window—dwarfs that of the actual instruction execution hardware and has become the predominant factor in determining the maximum operating frequency. Being wire-dominated, these structures also benefit less from technology scaling than the execution circuitry, increasing the importance of this problem. Value communication structures are complex because they are overly general. Each of these structures is built to support the most general possible communication pattern for each value. However, examining value communication in actual programs reveals that most values are involved in simple communication, such as producer to single consumer. This dissertation pro-poses an alternate model for inter-instruction register value communication in which values may be handled differently by mechanisms optimized to their individual needs. The foundation for this model is knowledge of communication on a per-value basis. The com-munication resource requirements of a value are summarized by its degree of use, which is simply