Asynchronous interface ASIC Flow (RTL-to-GDSII) using cadence and synopsys Tools
Tejas Raval · CSUN ScholarWorks (California State University, Northridge) · 2012
This project work would not have been possible without the guidance and the help of several individuals who in one way or another contributed and extended their valuable assistance in the preparation and completion of this project.First and foremost, my utmost gratitude to Dr. Ramin Roosta, Dr. Roosta has been my inspiration as I hurdle all the obstacles in the completion this project.Dr. Roosta's continuous guidance, support and resourcefulness in the field of ASIC/FPGA designing and verification helped to conquer every big and small milestone.Without his constant support and help this project would not have been materialized.It was an honor for me to work under his