Fpga Implementation of 2-D DCT Architecture for JPEG Image Compression
Prashant Chaturvedi, Tarun Verma, Rita Jain · International journal of advanced electronics and communication systems · 2013
This paper presents the architecture and the VHDL design of a Two Dimensional Discrete Cosine Transform (2-D DCT) for JPEG image compression. This architecture is used as the core of a JPEG compressor and is the critical path in JPEG compression hardware. Many algorithms and VLSI architectures for the fast computation of DCT have been proposed [10,11,12] The 2-D DCT calculation is made using the 2-D DCT separability property, such that the whole architecture is divided into two 1-D DCT calculations by using a transpose buffer. These parts are described in this paper, with an architectural discussion and the VHDL synthesis results as well. The 2-D DCT architecture uses 5,651 logic cells of one Spartan3 FPGA and reaches an operating frequency of 123 MHz. One input block with 8×8 elements of 8 bits each is processed in 5.2 μs and the pipeline latency is 160 clock cycles. This paper provides the architectural view and FPGA implementation of 2D-DCT for JPEG image compression .