Detecting and exploiting causal relationships in hardware shared-memory multiprocessors
Harold W. Cain, Mikko H. Lipasti · 2004
This thesis focuses on mechanisms that improve inter-processor communi-cation in hardware shared-memory multiprocessors by detecting and exploiting knowledge of the causal relationships among inter-processor reads and writes to shared memory. We present two applications for exploiting causal dependence knowledge: the avoidance of replays in a novel value-based memory ordering mechanism, and the avoidance of coherence misses in an invalidation-based coher-ence protocol. Conventional out-of-order processors employ a multiported, fully-associa-tive load queue to guarantee correct memory reference order both within a single thread of execution and across threads in a multiprocessor system. As improve-ments in process technology and pipelining lead to higher clock frequencies, scal-ing this complex structure to accommodate a larger number of in-flight loads becomes difficult. The value-based memory ordering mechanism presented here solves the associative load queue scalability problem by completely eliminating