An Efficient Architecture for Spiral-Type Motion Estimation for H.264/AVC
Naoyuki Hirai, Takahiro A. Kato, Tian Song, Takashi Shimamoto · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2009
New features of motion compensation, such as variable block size and multiple reference frames are introduced in H.264/AVC. However, it induces significant complexity increase. In this paper, an efficient architecture for spiral-type ME is proposed. First, we propose a hardware-friendly spiral search order. Then, an improved processing element (PE) architecture for ME is proposed to achieve the proposed search order. The improved PE enables the shift of the reference pixel data to top, bottom, right, and left by four input and output ports. Moreover, the parallel calculation architecture to calculate all block size with the SAD of 4×4 is introduced in the proposed architecture. As a result of hardware implementation, the hardware cost is about 145k gates. Maximum clock frequency is 134㎒ in the case of FPGA(Xilinx Vertex5) implementation.