Software engineering considerations in the design and implementation of a minicomputer-based digital logic circuit timing simulator.
Brenda M. Csencsits · 1978
A computer program chat simulates the fault-free behavior of logic circuits using a variable delay timing model is Implemented on the HP 21M-series minicomputer under the Hewlett-Packard RTE-III operating system. The circuit is described as an interconnection of logic gates, each of which may be assigned its own propagation delays: its nominal high-to-low delay and its nominal low-to-high delay. The simulation program reports circuit oscillations, spikes, and critical races in flip-flops. Considerations of implementation of such a program on a minicomputer are discussed. These include low computer cost, limited memory, slower machine cycle time, efficient data structure, and slower input-output on secondary storage. Software engineering considerations are discussed. The simulator is a FORTRAN program which is modular, uses data access routines, and is structured by pseudo-language comments. The work reported here was the author's work assignment carried out at Bell Laboratories, Allentovn, Pennsylvania, during 1977-1978.