Timing Estimation Method for Parame terized Macro Model Considering Pin-to-Pin Delay in High-Level Synthesis
Hyung Gyun Yang, Seon Wook Kim, Young Hwan Kim · ICEIC : International Conference on Electronics, Informations and Communications · 2008
To efficiently estimate the timing of a design in high-level synthesis (HLS), the timing information of a macro model should be characterized for various bit-widths. This paper presents a new parameterized timing model for accurate and efficient timing estimation in high-level circuit design. The proposed timing estimation method can estimate the timing information for all bits of modules by deducing from only a small number of macros’ timing information. Therefore, the proposed method has the advantages of the short characterization time of the timing library and the small size of the timing library. Experimental results on several parameterized macro modules with various architectures and bit-widths show that the timing estimation using the proposed model reveals the average error of 3.19%.