Development of a fast DRAM Analyzer and Measurement of Typical and Critical Memory Access Sequences in Applications
Simon Albert · 2008
The performance of current computer systems is highly influenced by the memory system. Today memory controllers have to adhere to a dozen SDRAM timing parameters which have to be fulfilled, in order to operate the SDRAM within its specification. For the thesis a measurement system was developed, which is capable of recording long access sequences in realtime without affecting system operation. From the gathered access sequences, those SDRAM parameters were determined which limit the system performance most significantly. For these SDRAM timings a statistical model was derived to estimate the impact of SDRAM timing parameter changes on the system performance. The estimates of the statistical model were then compared with measurements on the real system.