The Implementation of an Extensible PDP-11
GR Hellestrand, RA van der Laan · 1978
The implementation of a computer having the complexity of a PDP-11 has been a daunting task. The availability and increasing useability of configurable (microprogrammable) microprocessors has transformed the task into one which, although not insignificant, is no longer formidable. This paper describes the implementation of a PDP-11 computer using the AMD2900 microprogrammable microprocessor chip set. Considerable effort was expended in achieving a well-structured architecture, in which the organisation of the microinstruction word was deemed of paramount importance. The machine displays a modular architecture and, much of the combinational decoding logic may be realised by using programmed logic arrays. Basing the PDP-11 upon a microprogrammable microprocessor has been effective in that the machine may be described in a relatively short time and the resulting implementation is of modest cost. The projected speed of this machine is approximately 50% of that of the PDP-11 model 40, with some instruction execution speeds exceeding those of the model 40. There is a marked superiority in performance by this machine when compared with the DEC LS1-11 processor.