Analyzing CUDA’s Compiler through the Visualization of Decoded GPU Binaries
Cedric Nugteren, Bart Mesman, Henk Corporaal · 2012
With GPU architectures becoming increasingly important due to their large number of parallel processors, NVIDIA’s CUDA environment is becoming widely used to support gen-eral purpose applications. To efficiently use the parallel pro-cessing power, programmers need to efficiently parallelize and map their algorithms. The difficulty of this task leads to the idea to investigate CUDA’s compiler. Part of the compiler in the CUDA tool-chain is entirely un-documented, as is its output. To draw conclusions on the behaviour of this compiler, the resulting object code is re-verse engineered. A visualization tool is introduced, analyz-ing the previously unknown compiler behaviour and proving helpful to improve the mapping process for the programmer. These improvements focus on the area of register allocation and instruction reordering. This paper describes an exten-sion to the CUDA tool-chain, providing programmers with a visualization of register life ranges. Also, the paper presents guidelines describing how to apply optimizations in order to obtain a lower register pressure. In a case-study example, performance increases by 33 % com-pared to already optimized CUDA code. This is achieved by optimizing the code with the help of the introduced visual-ization tool. Also, in 11 other case-study examples, register pressure is reduced by an average of 18%. The presented guidelines could be added to the compiler to enable a simi-lar register pressure reduction to be achieved automatically at compile-time for new and existing CUDA programs.